The invention relates to a bias circuit used for implementing a BiCMOS input buffer and, more generally, to a circuit for establishing a temperature compensated voltage at one or more nodes within an electrical circuit or system.
A BiCMOS circuit is implemented with a technology that is the result of merging the separate Bipolar and CMOS manufacturing technologies. This BiCMOS technology allows circuit designs to combine the individual performance advantages of Bipolar and CMOS transistors. Bipolar transistors are best suited for switching high current signals that are encountered when interfacing or connecting the outputs of one integrated circuit function with other circuits comprising an electrical system. CMOS transistors are best suited for implementing functions that are internal to an integrated circuit, where small feature size and low power consumption are desirable.
When Bipolar transistors are used to drive the output signals of an integrated circuit function, the interfacing logic standard that is adopted is typically one that is optimum for Bipolar designs. Most notable are the TTL and ECL logic standards. Optimum circuit designs using CMOS transistors, however, are not compatible with TTL or ECL signal voltage levels are the input interface, and must be buffered with conversion circuitry. An input buffer circuit that converts Bipolar signal voltage levels into CMOS signal voltage levels is typically not an optimum design for either Bipolar or CMOS transistors, and deserves special attention by the designer.
A typical TTL-to-CMOS input conversion buffer configuration is shown in FIG. 1. This circuit form employs a bias circuit, F, which modifies the behavior of the CMOS inverter stage, M1 and M2. For a standard CMOS design, the characteristic input threshold voltage, of the Ml and M2 inverter stage, would be equal to one half of the Vcc voltage, or approximately 2.5V. The addition of bias circuit, F, at node "B", between Vcc and Ml, lowers the input threshold voltage to the TTL level of approximately 1.4V. In addition, the bias circuit receives a feedback signal from node "C", the non-inverting output of the buffer, for the purpose of creating hysteresis in the input threshold voltage behavior. Hysteresis causes the threshold voltage, for a signal that is transitioning high-to-low, to be lower than the threshold voltage for a signal transitioning low-to-high. A typical hysteresis value of 200mV would result in a nominal high-to-low transition threshold equal to 1.3V, and a nominal low-to-high transition threshold equal to 1.5V. Hysteresis is typically utilized in TTL-to-CMOS converter circuits to eliminate well-known CMOS switching instabilities.
Prior art methods of implementing the bias circuit, F, in a TTL-to-CMOS converter, are shown in FIGS. 2 and 3. The configuration shown in FIG. 2 is a carry-over from pure CMOS technologies, in which Bipolar devices were not available. During high-to-low input signal transitions, transistor M5 is initially "off", and the behavior of the bias circuit is determined by transistor M6. Conversely, during low-to-high signal transitions, transistor M5 is initially "on", shunting the effect of M6 and dominating the behavior of the bias circuit. The individual sizes of transistors M5 and M6, and their relationship to the sizes of transistors Ml and M2, determine the threshold voltages and the amount of resulting hysteresis. The configuration of FIG. 2, however, has been typically abandoned in favor of the configuration shown in FIG. 3. Replacing transistor M6 with junction diodes, D1 and D2, results in input threshold voltage characteristics that are less sensitive to manufacturing variations in the CMOS transistor parameters. In addition, diodes D1 and D2 contribute to a faster signal propagation time during the high-to-low input transition phase.
The introduction of the Bipolar junction diodes into the CMOS circuit, as shown in FIG. 3, yields a typical input threshold characteristic as shown graphically in FIG. 4. The chart displays input threshold voltage as a function of Temperature for both the low-to-high transition and the high-to-low transition. The chart also highlights the 0.8V and 2.OV TTL threshold specification limits. The threshold voltage of the buffer must be guaranteed to be between these limits over the operating voltage and temperature range of the integrated circuit. It can be seen from this chart, that the high-to-low transition threshold increases with increasing temperature (positive temperature coefficient), while the low-to-high transition threshold decreases with increasing temperature (negative temperature coefficient). These contrary threshold slopes cause the amount of hysteresis, the difference between the two thresholds, to rapidly diminish as the temperature increases. The primary cause of this behavior is that the high-to-low transition threshold is determined by the Bipolar junction diodes D1 and D2, which have a negative voltage temperature coefficient, and the low-to-high transition threshold is determined by CMOS transistor M5, which has a positive drain-to-source voltage temperature coefficient. In order to prevent the magnitude of hysteresis from diminishing below a minimum acceptable design level at high temperatures, the thresholds at low temperatures must be set unacceptably close to the TTL specification limits. If the voltage temperature coefficient magnitude of the Bipolar junction diodes could be reduced, or "compensated", then the resulting input threshold temperature characteristic slopes would be similar. The benefits of this compensated behavior would be, that the amount of hysteresis would change very little over temperature, and this would result in input threshold voltage characteristics that could be set to a greater margin within the TTL specification limits. A design with this desirable behavior has the advantage of being more tolerant of manufacturing variations, and hence, more conducive to higher manufacturing yields of the integrated circuit.
Accordingly, it is the object of this invention to provide a novel temperature compensated bias circuit. It is a further object of this invention to provide a temperature compensated bias circuit for a high performance TTL-to-CMOS input buffer implemented in the BiCMOS technology. It is a further object, still, of this invention, to provide a temperature compensated circuit that may be used throughout an electronic circuit or electronic system comprising a plurality of circuits.